1. Field of the Invention
The present invention relates to a semiconductor devices and related methods, and more particularly, to contact pad configurations and related methods.
2. Description of the Related Art
As semiconductor devices become more highly integrated, many changes and improvements have been made in the structure of capacitors and bit lines of semiconductor memory devices. In 256M DRAMs or greater, contacts for the connection of a drain and a storage electrode used as a lower electrode of a capacitor and the connection of a source and a bit line are typically formed by the formation of contact pads through a self-aligned process.
In such self-aligned formation of contacts and contact pads, a self-aligned contact pattern may be formed separately from the formation of gates, and contacts with the contact pads thereon may be formed between the gates using the self-aligried contact pattern as a mask. After formation of an inter-metallic dielectric film, contacts for the electrical connection of the bit line and the lower electrode of the capacitor may be formed in the inter-metallic dielectric film.
According to the above-described conventional methods, the lower electrode contact and the bit line contact are typically formed through different processes, resulting in many boundaries and a long contact path length. As a result, the contact resistance in a complete semiconductor memory device may be substantially high and short-circuiting may be likely to occur due to the introduction of dopants in the complicated manufacturing process. Therefore, the conventional techniques may lower the yield and reliability of semiconductor memory devices produced thereby.